Stress engineering techniques are employed to improve the performance of CMOS devices by applying a mechanical stress/strain to the channel region of FETs, with pFET devices requiring compressive stress and nFET devices requiring tensile stress. The applied stress enhances the mobility of the majority carriers (holes in pFET and electrons in nFET devices), enabling higher transistor drive currents and faster logic gate switching speeds.
Several techniques have been developed for applying the mechanical strain to the channel region of the FETs. One technique, which can create either tensile or compressive stress fields in the channel regions of CMOS devices, involves depositing nitride films at least over the gates covering the channel regions. However, only a fraction of the intrinsic film stress is transferred into the channel due the large distance between the nitride film and the channel. A second, more efficient technique is the so called embedded epitaxial silicon/germanium (eSi/Ge) technique. The expanding Si/Ge is formed in the source/drain regions very close to the channel. However, eSi/Ge is an expensive technique and, thus, is not well-suited for use with low-cost bulk planar CMOS.
A third technique for creating additional stress in the channel of MOSFET devices is the Stress Memory Technique (SMT). According to this technique, a first film with intrinsic stress is deposited over the device which, after thermal treatment, is removed. Due to not yet well understood processes, a portion of the exerted stress remains (i.e. is “memorized”) in the device. Then a second etch stop liner (ESL) film with intrinsic stress is deposited and, thus, a higher stress can be achieved in the device than with the ESL film alone. However, although SMT works well for nFET devices, it does not work for pFET devices.
A fourth technique for straining the channel region is to use a hetero structure of different layers (e.g. SiGe and Si layers) to form the device channel. For example, a relaxed SiGe layer is grown on top of a recessed Si substrate using epitaxial growth. On top of this relaxed layer, a strained Si layer is deposited. The strain in the Si layer stems from a lattice constant mismatch between Si and SiGe. The epitaxial process used to create these structures is very slow and expensive and, thus, has not found use in mainstream semiconductor fabrication. Alternatively, the formation of SiC by implantation and solid phase epitaxial regrowth for embedded SiC has been proposed for source and drain regions.
References describing the above mentioned techniques include:                1. T. Mizuno et al., Novel Anisotropic Strain Engineering on (110)-Surface SOI CMOS Devices using Combination of Local/Global Strain Techniques, IEDM 2006;        2. K.-W. Ang et al., Beneath-The-Channel Strain-Transfer-Structure (STS) and Embedded Source/Drain Stressors for Strain and Performance Enhancement of Nanoscale MOSFETs, 2007 Symposium on VLSI Technology; and        3. Y. Liu et al., Strained Si Channel MOSFETs with Embedded Silicon Carbon Formed by Solid Phase Epitaxy, 2007 Symposium on VLSI Technology.        
In view of the above, an improved method is needed for producing increased stress fields in MOSFETs.